View CS61574A_146404.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

CS61574A CS61575
T1/E1 Line Interface
Features General Description
The CS61574A and CS61575 combine the complete analog transmit and receive line interface for T1 or E1 applications in a low power, 28-pin device operating from a +5V supply. Both devices support processorbased or stand-alone operation and interface with industry standard T1 and E1 framers. The receiver uses a digital Delay-Locked-Loop which is continuously calibrated from a crystal reference to provide excellent stability and jitter tolerance. The CS61574A has a receiver jitter attenuator optimized for minimum delay in switching and transmission applications, while the CS61575 attenuator is optimized for CPE applications subject to AT&T 62411 requirements. The transmitter features internal pulse shaping and a matched, constant impedance output stage to insure signal quality on mismatched, poorly terminated lines.
*
Provides Analog Transmission Line Interface for T1 and E1 Applications
* Provides Line Driver, Jitter Attenuator
and Clock Recovery Functions
* Fully Compliant with AT&T 62411
Stratum 4 Jitter Requirements
* Low Power Consumption
(typically 175 mW)
* B8ZS/HDB3/AMI Encoder/Decoder * 14 dB of Transmitter Return Loss
( ) = Pin Function in Host Mode [ ] = Pin Function in Extended Hardware Mode 2 TCLK TPOS [TDATA] TNEG [TCODE] RCLK RPOS [RDATA] RNEG [BPV] 3 R E M O T E L O O P B A C K 26
Applications
* * *
Interfacing Network Equipment such as DACS and Channel Banks to a DSX-1 Cross Connect Interfacing Customer Premises Equipment to a CSU Building Channel Service Units
ORDERING INFORMATION - See page 26.
(CLKE) (INT) (SDI) (SDO) TAOS LEN0 LEN1 LEN2 28 23 24 25
MODE 5 L O C A L L O O P B A C K
TGND
TV+
15 14 LINE DRIVER 13 16
CONTROL
PULSE SHAPER LINE RECEIVER
TTIP TRING
4
8 7
AMI, B8ZS, HDB3, CODER
19 20 17
JITTER ATTENUATOR
CLOCK & DATA RECOVERY SIGNAL QUALITY MONITOR
RTIP
RRING MTIP [RCODE] MRING [PCS] DPM [AIS]
6
DRIVER MONITOR 22 RGND
18
11 9 10 1 27 LLOOP (SCLK) 12 LOS 21 RV+
RLOOP XTALIN XTALOUT ACLKI (CS)
Crystal Semiconductor Corporation P. O. Box 17847, Austin, Texas, 78760 (512) 445-7222 FAX:(512) 445-7581
Copyright (c) Crystal Semiconductor Corporation 1996 (All Rights Reserved)
MAY '96 DS154F2 1
CS61574A CS61575
ABSOLUTE MAXIMUM RATINGS
Symbol Min Max Units DC Supply RV+ 6.0 V TV+ (RV+) + 0.3 V Input Voltage, Any Pin (Note 1) Vin RGND-0.3 (RV+) + 0.3 V Input Current, Any Pin (Note 2) Iin -10 10 mA Ambient Operating Temperature TA -40 85 C Storage Temperature Tstg -65 150 C WARNING:Operations at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. Notes: 1. Excluding RTIP, RRING, which must stay within -6V to (RV+) + 0.3V. 2. Transient currents of up to 100 mA will not cause SCR latch-up. Also TTIP, TRING, TV+ and TGND can withstand a continuous current of 100 mA. Parameter (referenced to RGND, TGND=0V)
RECOMMENDED OPERATING CONDITIONS
Symbol Min Typ Max DC Supply (Note 3) RV+, TV+ 4.75 5.0 5.25 Ambient Operating Temperature TA -40 25 85 290 350 Power Consumption (Notes 4,5) PC Power Consumption (Notes 4,6) PC 175 Notes: 3. TV+ must not exceed RV+ by more than 0.3V. 4. Power consumption while driving line load over operating temperature range. Includes IC and Digital input levels are within 10% of the supply rails and digital outputs are driving a 50 pF capacitive load. 5. Assumes 100% ones density and maximum line length at 5.25V. 6. Assumes 50% ones density and 300ft. line length at 5.0V. Parameter Units V C mW mW load.
DIGITAL CHARACTERISTICS
Parameter
(TA = -40C to 85C; TV+, RV+ = 5.0V 5%; GND = 0V) Symbol Min Typ Max Units V V V V A V V V
2.0 High-Level Input Voltage (Notes 7, 8) VIH PINS 1-4, 17, 18, 23-28 Low-Level Input Voltage (Notes 7, 8) VIL 0.8 PINS 1-4, 17, 18, 23-28 High-Level Output Voltage (Notes 7, 8, 9) VOH 4.0 IOUT = -40 A PINS 6-8, 11, 12, 25 0.4 Low-Level Output Voltage (Notes 7, 8, 9) VOL IOUT = 1.6 mA PINS 6-8, 11, 12, 23, 25 Input Leakage Current (Except Pin 5) 10 Low-Level Input Voltage, PIN 5 VIL 0.2 High-Level Input Voltage, PIN 5 VIH (RV+) - 0.2 Mid-Level Input Voltage, PIN 5 (Note 10) VIM 2.3 2.7 Notes: 7. In Extended Hardware Mode, pins 17 and 18 are digital inputs. In Host Mode, pin 23 is an open drain output and pin 25 is a tristate output. 8. This specification guarantees TTL compatibility (VOH = 2.4V @ IOUT = -40A). 9. Output drivers will drive CMOS logic levels into a CMOS load. 10. As an alternative to supplying a 2.3-to-2.7V input, this pin may be left floating. 2
DS154F2
CS61574A CS61575
ANALOG SPECIFICATIONS
Parameter
(TA = -40C to 85C; TV+, RV+ = 5.0V 5%; GND = 0V) Min Typ Max Units
Transmitter AMI Output Pulse Amplitudes (Note 11) 2.14 2.37 2.6 V E1, 75 (Note 12) 2.7 3.0 3.3 V E1, 120 (Note 13) 2.7 3.0 3.3 V T1, FCC Part 68 (Note 14) 2.4 3.0 3.6 V T1, DSX-1 (Note 15) E1 Zero (space) level (LEN2/1/0 = 0/0/0) -0.237 0.237 V 1:1 transformer and 75 load -0.3 0.3 V 1:1.26 transformer and 120 load Recommended Output Load at TTIP and TRING 75 Jitter Added During Remote Loopback (Note 16) 10Hz - 8kHz 0.005 0.02 UI 8kHz - 40kHz 0.008 0.025 UI 0.010 0.025 UI 10Hz - 40kHz 0.015 0.05 UI Broad Band Power in 2kHz band about 772kHz (Notes 11, 17) 12.6 15 17.9 dBm Power in 2kHz band about 1.544MHz (Notes 11, 17) -29 -38 dB (referenced to power in 2kHz band at 772kHz) Positive to Negative Pulse Imbalance (Notes 11, 17) T1, DSX-1 0.2 0.5 dB E1 amplitude at center of pulse -5 5 % -5 5 % E1 pulse width at 50% of nominal amplitude Transmitter Return Loss (Notes 11, 17, 18) 51 kHz to 102 kHz 8 dB 102 kHz to 2.048 MHz 14 dB 2.048 MHz to 3.072 MHz 10 dB Transmitter Short Circuit Current (Notes 11, 19) 50 mA RMS Driver Performance Monitor MTIP/MRING Sensitivity: Differential Voltage Required for Detection 0.6 V Notes: 11. Using a 0.47 F capacitor in series with the primary of a transformer recommended in the Applications section. 12. Pulse amplitude measured at the output of a 1:1 or 1:1.26 transformer across a 75 load for line length setting LEN2/1/0 = 0/0/0. 13. Pulse amplitude measured at the output of a 1:1.26 transformer across a 120 load for line length setting LEN2/1/0 = 0/0/0. 14. Pulse amplitude measured at the output of a 1:1.15 transformer across a 100 load for line length setting LEN2/1/0 = 0/1/0. 15. Pulse amplitude measured at the DSX-1 cross-connect across a 100 load for line length settings LEN2/1/0 = 0/1/1, 1/0/0, 1/0/1, 1/1/0, or 1/1/1 using a 1:1.15 transformer and the length of #22 AWG, ABAM, or equivalent cable specified in Table 3. 16. Input signal to RTIP/RRING is jitter free. Values will reduce slightly if jitter free clock is input to TCLK. 17. Not production tested. Parameters guaranteed by design and characterization. 18. Return loss = 20 log10 ABS((z1 +z0)/(z1-z0)) where z1 = impedance of the transmitter, and z0 = impedance of line load. Measured with a repeating 1010 data pattern with LEN2/1/0 = 0/0/0 and a 1:1 transformer terminated with a 75 load, or a 1:1.26 transformer terminated with a 120 load. 19. Measured broadband through a 0.5 resistor across the secondary of a 1:1.26 transformer during the transmission of an all ones data pattern for LEN2/1/0 = 0/0/0.
DS154F2 3
CS61574A CS61575
ANALOG SPECIFICATIONS
Parameter
(TA = -40C to 85C; TV+, RV+ = 5.0V 5%; GND = 0V) Min -13.6 500 Typ 50k Max Units dB mV
Receiver RTIP/RRING Input Impedance Sensitivity Below DSX (0dB = 2.4V)
Data Decision Threshold T1, DSX-1 (Note 20) 60 65 70 % of peak T1, DSX-1 (Note 21) 53 65 77 % of peak T1, FCC Part 68 and E1 (Note 22) 45 50 55 % of peak Allowable Consecutive Zeros before LOS 160 175 190 bits Receiver Input Jitter Tolerance (Note 23) 10kHz - 100kHz 0.4 UI 6.0 UI 2kHz 10Hz and below 300 UI Loss of Signal Threshold (Note 24) 0.25 0.30 0.50 V Notes: 20. For input amplitude of 1.2 Vpk to 4.14 Vpk. 21. For input amplitude of 0.5 Vpk to 1.2 Vpk and from 4.14 Vpk to RV+. 22. For input amplitude of 1.05 Vpk to 3.3 Vpk. 23. Jitter tolerance increases at lower frequencies. See Figure 11. 24. The analog input squelch circuit shall operate when the input signal amplitude above ground on the RTIP and RRING pins falls within the range of 0.25V to 0.50V. Operation of the squelch results in the recovery of zeros. During receive LOS, the RPOS, RNEG or RDATA outputs are forced low.
4
DS154F2
CS61574A CS61575
ANALOG SPECIFICATIONS
Parameter
(TA = -40C to 85C; TV+, RV+ = 5.0V 5%; GND = 0V) Min Typ Max Units
Jitter Attenuator Jitter Attenuation Curve Corner Frequency (Notes 17, 25) CS61574A 6 Hz CS61575 3 Hz CS61574A T1 Receiver Jitter Transfer (Notes 25, 26) Jitter Freq. [Hz] Amplitude [UIpp] 10 10 3.0 6.0 dB 20 30 dB 100 10 500 10 35 40 dB 40 50 dB 1k 5 40 50 dB 10k, 40k 0.3 CS61575 T1 Receiver Jitter Transfer (Notes 25, 26) Jitter Freq. [Hz] Amplitude [UIpp] 6.0 9.0 dB 10 10 100 10 23 33 dB 500 10 38 43 dB 40 50 dB 1k 5 40 50 dB 10k, 40k 0.3 CS61574A E1 Receiver Jitter Transfer (Notes 26, 27, 28) Jitter Freq. [Hz] Amplitude [UIpp] 10 1.5 3.0 6.0 dB 20 1.5 6.0 12 dB 20 32 dB 100 1.5 30 40 dB 400 1.5 1k 1.5 35 45 dB 35 45 dB 10k, 100k 0.2 CS61575 E1 Receiver Jitter Transfer (Notes 26, 27, 28) Jitter Freq. [Hz] Amplitude [UIpp] 10 1.5 6.0 12 dB 12 18 dB 20 1.5 100 1.5 22 29 dB 30 39 dB 400 1.5 35 45 dB 1k 1.5 10k, 100k 0.2 35 45 dB Attenuator Input Jitter Tolerance (Notes 17, 28) (Before Onset of FIFO Overflow or Underflow Protection) CS61574A 12 23 UI CS61575 138 UI Notes: 25. Attenuation measured at the demodulator output of an HP3785B with input jitter equal to 3/4 of measured jitter tolerance using a measurement bandwidth of 1 Hz (10 1kHz) centered around the jitter frequency. With a 2 -1 PRBS data pattern. 26. Crystal must meet specifications described in CXT6176/CXT8192 data sheet. 27. Jitter measured at the demodulator output of an HP3785A (or equivalent) using a measurement bandwidth not to exceed 20 Hz centered around the jitter frequency. With a 215-1 PRBS data pattern. 28. Jitter below 100 kHz and within the attenuator's input jitter tolerance is not translated or aliased to other frequencies. Output jitter increases significantly when attenuator input jitter tolerance is exceeded.
DS154F2
5
CS61574A CS61575
T1 SWITCHING CHARACTERISTICS
Parameter
(TA = -40C to 85C; TV+, RV+ = 5.0V 5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3) Symbol Min Typ Max 500 60 55 85 85 Units MHz MHz ns % MHz % ns ns ns ns ns ns ns ns ns ns
6.176000 Crystal Frequency (Note 26) fc TCLK Frequency ftclk 1.544 TCLK Pulse Width (Note 29) tpwh2 150 ACLKI Duty Cycle tpwh3/tpw3 40 ACLKI Frequency (Note 30) faclki 1.544 RCLK Duty Cycle (Note 31) tpwh1/tpw1 45 50 Rise Time, All Digital Outputs (Note 32) tr Fall Time, All Digital Outputs (Note 32) tf TPOS/TNEG (TDATA) to TCLK Falling Setup Time tsu2 25 TCLK Falling to TPOS/TNEG (TDATA) Hold Time th2 25 RPOS/RNEG Valid Before RCLK Falling (Note 33) tsu1 150 274 RDATA Valid Before RCLK Falling (Note 34) tsu1 150 274 RPOS/RNEG Valid Before RCLK Rising (Note 35) tsu1 150 274 RPOS/RNEG Valid After RCLK Falling (Note 33) th1 150 274 RDATA Valid After RCLK Falling (Note 34) th1 150 274 RPOS/RNEG Valid After RCLK Rising (Note 35) th1 150 274 Notes: 29. The transmitted pulse width does not depend on the TCLK duty cycle. 30. ACLKI provided by an external source or TCLK. 31. RCLK duty cycle will be 62.5% or 37.5% when jitter attenuator limits are reached. 32. At max load of 1.6 mA and 50 pF. 33. Host Mode (CLKE = 1). 34. Extended Hardware Mode. 35. Hardware Mode, or Host Mode (CLKE = 0).
E1 SWITCHING CHARACTERISTICS
Parameter
(TA = -40C to 85C; TV+, RV+ = 5.0V 5%;
GND = 0V; Inputs: Logic 0 = 0V, Logic 1 = RV+; See Figures 1, 2, & 3) Symbol 26) 29) 30) 31) 32) 32) fc ftclk tpwh2 tpwh3/tpw3 faclki tpwh1/tpw1 tr tf tsu2 th2 tsu1 tsu1 tsu1 th1 th1 th1 Min 150 40 45 25 25 100 100 100 100 100 100 Typ 8.192000 2.048 2.048 50 194 194 194 194 194 194 Max 340 60 55 85 85 Units MHz MHz ns % MHz % ns ns ns ns ns ns ns ns ns ns DS154F2
Crystal Frequency (Note TCLK Frequency TCLK Pulse Width (Note ACLKI Duty Cycle ACLKI Frequency (Note RCLK Duty Cycle (Note Rise Time, All Digital Outputs (Note Fall Time, All Digital Outputs (Note TPOS/TNEG (TDATA) to TCLK Falling Setup Time TCLK Falling to TPOS/TNEG (TDATA) Hold Time RPOS/RNEG Valid Before RCLK Falling (Note RDATA Valid Before RCLK Falling (Note RPOS/RNEG Valid Before RCLK Rising (Note RPOS/RNEG Valid After RCLK Falling (Note RDATA Valid After RCLK Falling (Note RPOS/RNEG Valid After RCLK Rising (Note 6
33) 34) 35) 33) 34) 35)
CS61574A CS61575
SWITCHING CHARACTERISTICS
Inputs: Logic 0 = 0V, Logic 1 = RV+) Parameter SDI to SCLK Setup Time SCLK to SDI Hold Time SCLK Low Time SCLK High Time SCLK Rise and Fall Time CS to SCLK Setup Time SCLK to CS Hold Time CS Inactive Time SCLK to SDO Valid CS to SDO High Z Input Valid To PCS Falling Setup Time PCS Rising to Input Invalid Hold Time PCS Active Low Time Notes: 36. Output load capacitance = 50pF.
(TA = -40 to 85C; TV+, RV+ = 5%;
Symbol tdc tcdh tcl tch tr, tf tcc tcch tcwh tcdv tcdz tsu4 th4 tpcsl
Min 50 50 240 240 50 50 250 50 50 250
Typ 100 -
Max 50 200 -
Units ns ns ns ns ns ns ns ns ns ns ns ns ns
(Note 36)
tr
tf
Any Digital Output
90%
10%
90%
10%
Figure 1. Signal Rise and Fall Characteristics
tpw1 RCLK t pwl1 t su1 t pwh1 t h1 EXTENDED HARDWARE MODE OR HOST MODE (CLKE = 1)
RPOS RNEG RDATA BPV RCLK
HARDWARE MODE OR HOST MODE (CLKE = 0)
Figure 2. Recovered Clock and Data Switching Characteristics
DS154F2
7
CS61574A CS61575
t pw2 t pwh2 TCLK t su2 t h2
ACLKI
Figure 3b. Alternate External Clock Characteristics
t cwh CS
t pw3 t pwh3
TPOS/TNEG
Figure 3a. Transmit Clock and Data Switching Characteristics
t cc
SCLK t dc SDI
t ch
t cl
t cch
t cdh LSB
BYTE DATA BYTE
t cdh MSB
LSB
CONTROL
Figure 4. Serial Port Write Timing Diagram
CS
t cdz
SCLK t cdv SDO CLKE = 1
Figure 5. Serial Port Read Timing Diagram
HIGH Z
PCS t su4 LEN0/1/2, TAOS, RLOOP, LLOOP, RCODE, TCODE t pcsl
VALID INPUT DATA
th4
Figure 6. Extended Hardware Mode Parallel Chip Select Timing Diagram
8
DS154F2
CS61574A CS61575
THEORY OF OPERATION Enhancements in CS61575 and CS61574A The CS61574A and CS61575 provide higher performance and more features than the CS61574 including: * * * * * * * * AT&T 62411, Stratum 4 compliant jitter attenuation over the full range of operating frequency and jitter amplitude (CS61575), 50% lower power consumption, Internally matched transmitter output impedance for improved signal quality, Optional AMI, B8ZS, HDB3 encoder/decoder or external line coding support, Receiver AIS (unframed all ones) detection, ANSI T1.231-1993 compliant receiver LOS (Loss of Signal) handling, Transmitter TTIP and TRING outputs are forced low when TCLK is static, The Driver Performance Monitor operates over a wider range of input signal levels.
Introduction to Operating Modes The CS61574A and CS61575 support three operating modes which are selected by the level of the MODE pin as shown in Tables 1 and 2, Figure 7, and Figures A1-A3 of the Applications section. The modes are Hardware Mode, Extended Hardware Mode, and Host Mode. In Hardware and Extended Hardware Modes, discrete pins are used to configure and monitor the device. The Extended Hardware Mode provides a parallel chip select input which latches the control inputs allowing individual ICs to be configured using a common set of control lines. In the Host Mode, an external processor monitors and configures the device through a serial interface. There are thirteen multi-function pins whose functionality is determined by the operating mode. (see Table 2).
Hardware Mode Control Method MODE Pin Level Line Coding AIS Detection Driver Performance Monitor Control Pins <0.2 V Extended Host Hardware Mode Mode Control Pins Serial with Parallel Interface Chip Select Floating or >(RV+)-0.2 2.5 V V InternalAMI, B8ZS, or HDB3 Yes No External
Existing designs using the CS61574 can be converted to the higher performance, pin-compatible CS61574A or CS61575 if the transmit transformer is replaced by a pin-compatible transformer with a new turns ratio. Understanding the Difference Between the CS61575 and CS61574A The CS61574A and CS61575 provide receiver jitter attenuation performance optimized for different applications. The CS61575 is optimized to attenuate large amplitude, low frequency jitter for T1 Customer Premises Equipment (CPE) applications as required by AT&T 62411. The CS61574A is optimized to minimize data delay in T1 and E1 switching or transmission applications. Refer to the "Jitter Attenuator" section for additional information.
External
No Yes
No Yes
Table 1. Differences Between Operating Modes
DS154F2
9
CS61574A CS61575
HARDWARE MODE
TAOS LLOOP RLOOP LEN0/1/2
CONTROL TPOS TNEG CS62180B FRAMER CIRCUIT LINE DRIVER TTIP TRING MRING MTIP DPM RTIP LINE RECEIVER RRING
TRANSMIT TRANSFORMER
CS61575 CS61574A
RPOS RNEG JITTER ATTENUATOR
DRIVER MONITOR
RECEIVE TRANSFORMER
EXTENDED HARDWARE MODE
TCODE RCODE TAOS LLOOP RLOOP PCS LEN0/1/2
CONTROL TTIP TDATA T1 or E1 REPEATER OR MUX RDATA AMI B8ZS, HDB3, CODER LINE DRIVER TRING TRANSMIT TRANSFORMER
CS61575 CS61574A
RTIP
AIS DETECT
JITTER ATTENUATOR
LINE RECEIVER
RRING
RECEIVE TRANSFORMER
BPV
AIS
P SERIAL PORT 5
HOST MODE
CLKE
CONTROL TPOS TNEG CS62180B FRAMER CIRCUIT RPOS RNEG
CONTROL TTIP LINE DRIVER MRING MTIP DPM RTIP LINE RECEIVER RRING TRING TRANSMIT TRANSFORMER
CS61575 CS61574A
JITTER ATTENUATOR
DRIVER MONITOR
RECEIVE TRANSFORMER
Figure 7. Overview of Operating Modes
10
DS154F2
CS61574A CS61575
MODE EXTENDED FUNCTION PIN HARDWARE HARDWARE 3 TPOS TDATA TRANSMITTER TCODE 4 TNEG 6 RNEG BPV 7 RPOS RDATA RECEIVER/DPM 11 DPM AIS RCODE 17 MTIP 18 MRING 18 PCS 23 LEN0 LEN0 24 LEN1 LEN1 CONTROL 25 LEN2 LEN2 26 RLOOP RLOOP 27 LLOOP LLOOP 28 TAOS TAOS
NORMALIZED AMPLITUDE
HOST TPOS TNEG RNEG RPOS DPM MTIP MRING INT SDI SDO CS SCLK CLKE
1.0
ANSI TI.102, AT&T CB 119 SPECIFICATIONS
0.5
0 OUTPUT PULSE SHAPE
-0.5
0 250 500 750 TIME (nanoseconds) 1000
Table 2. Pin Definitions
Figure 8. Typical Pulse Shape at DSX-1 Cross Connect
Transmitter The transmitter takes digital T1 or E1 input data and drives appropriately shaped bipolar pulses onto a transmission line. The transmit data (TPOS & TNEG or TDATA) is supplied synchronously and sampled on the falling edge of the input clock, TCLK. Either T1 (DSX-1 or Network Interface) or E1 CCITT G.703 pulse shapes may be selected. Pulse shaping and signal level are controlled by "line length select" inputs as shown in Table 3.
The CS61575 and CS61574A line drivers are designed to drive a 75 equivalent load. For E1 applications, the CS61574A and CS61575 drivers provide 14 dB of return loss during the transmission of both marks and spaces. This improves signal quality by minimizing reflections off the transmitter. Similar levels of return loss are provided for T1 applications. For T1 DSX-1 applications, line lengths from 0 to 655 feet (as measured from the transmitter to the DSX-1 cross connect) may be selected. The five partition arrangement in Table 3 meets ANSI T1.102 and AT&T CB-119 requirements when using #22 ABAM cable. A typical output pulse is shown in Figure 8. These pulse settings can also be used to meet CCITT pulse shape requirements for 1.544 MHz operation. For T1 Network Interface applications, two additional options are provided. Note that the optimal pulse width for Part 68 (324 ns) is narrower than the optimal pulse width for DSX-1 (350 ns). The CS61575 and CS61574A automatically adjusts the pulse width based upon the "line length" selection made.
LEN2 LEN1 LEN0 0 1 1 1 0 0 1 0 1 1 1 0 1 1 1 0 0 0 0 0 0 0 1 1 1 0 1
Option Selected Application 0-133 FEET DSX-1 133-266 FEET ABAM 266-399 FEET (AT&T 600B 399-533 FEET or 600C) 533-655 FEET E1 120 (1:1.26) CCITT G.703 75 (1:1) AT&T CB113 Repeater FCC PART 68, OPT. A Network Interface ANSI T1.403
Table 3. Line Length Selection
DS154F2
11
CS61574A CS61575
Percent of nominal peak voltage 120
269 ns
when RLOOP is selected because the timing circuitry must adjust to the new frequency. Transmit All Ones Select The transmitter provides for all ones insertion at the frequency of TCLK. Transmit all ones is selected when TAOS goes high, and causes continuous ones to be transmitted on the line (TTIP and TRING). In this mode, the TPOS and TNEG (or TDATA) inputs are ignored. If Remote Loopback is in effect, any TAOS request will be ignored. Receiver The receiver extracts data and clock from an AMI (Alternate Mark Inversion) coded signal and outputs clock and synchronized data. The receiver is sensitive to signals over the entire range of ABAM cable lengths and requires no equalization or ALBO (Automatic Line Build Out) circuits. The signal is received on both ends of a centertapped, center-grounded transformer. The transformer is center tapped on the IC side. The clock and data recovery circuit exceeds the jitter tolerance specifications of Publications 43802, 43801, AT&T 62411, TR-TSY-000170, and CCITT REC. G.823.
110
100 90
244 ns
194 ns
80
50
10
0
Nominal Pulse
-10
-20 219 ns 488 ns
Figure 9. Mask of the Pulse at the 2048 kbps Interface
The E1 G.703 pulse shape is supported with line length selection LEN2/1/0=0/0/0. The pulse width will meet the G.703 pulse shape template shown in Figure 9, and specified in Table 4. The CS61574A and CS61575 will detect a static TCLK, and will force TTIP and TRING low to prevent transmission when data is not present. When any transmit control pin (TAOS, LEN0-2 or LLOOP) is toggled, the transmitter outputs will require approximately 22 bit periods to stabilize. The transmitter will take longer to stabilize
Nominal peak voltage of a mark (pulse) Peak voltage of a space (no pulse) Nominal pulse width Ratio of the amplitudes of positive and negative 0.95 to 1.05* pulses at the center of the pulse interval Ratio of the widths of positive and negative 0.95 to 1.05* pulses at the nominal half amplitude * When configured with a 0.47 F nonpolarized capacitor in series with the TX transformer primary as shown in Figures A1, A2 and A3. Table 4. CCITT G.703 Specifications 12
For c oax ia l c able, For shielded twisted 75 loa d a nd pair, 120 load and transformer specified transformer specified in Application Section. in Application Section. 2.37 V 3V 0 0.237 V 0 0.30 V 244 ns
DS154F2
CS61574A CS61575
RTIP 1:2
Data Level Slicer
RRING
Data Sampling & Clock Extraction
RPOS
Jitter Attenuator
RNEG RCLK
Edge Detector
Clock Phase Selector
Continuously Calibrated Delay Line
Figure 10. Receiver Block Diagram
A block diagram of the receiver is shown in Figure 10. The two leads of the transformer (RTIP and RRING) have opposite polarity allowing the receiver to treat RTIP and RRING as unipolar signals. Comparators are used to detect pulses on RTIP and RRING. The comparator thresholds are dynamically established at a percent of the peak level (50% of peak for E1, 65% of peak for T1; with the slicing level selected by LEN2/1/0 inputs). The leading edge of an incoming data pulse triggers the clock phase selector. The phase selector chooses one of the 13 available phases which the delay line produces for each bit period. The output from the phase selector feeds the clock and data recovery circuits which generate the recovered clock and sample the incoming signal at appropriate intervals to recover the data. Data sampling will continue at the periods selected by the phase selector until an incoming pulse deviates enough to cause a new phase to be selected for data sampling. The phases of the delay line are selected and updated to allow as much as 0.4 UI of jitter from 10 kHz to 100 kHz, without error. The jitter tolerance of the receiver exceeds that shown in Figure 11. Additionally, this method of clock and data recovery is tolerant of long strings of consecutive zeros. The data
DS154F2
sampler will continuously sample data based on its last input until a new pulse arrives to update the clock phase selector. The delay line is continuously calibrated using the crystal oscillator reference clock. The delay line produces 13 phases for each cycle of the reference clock. In effect, the 13 phases are analogous to a 20 MHz clock when the reference clock is 1.544 MHz. This implementation utilizes the benefits of a 20 MHz clock for clock recovery without actually having the clock present to impede analog circuit performance.
300 138 100 AT&T 62411 28 10 PEAK-TO-PEAK JITTER (unit intervals) 1 .4
Minimum Performance
.1
1
10
100 300 700 1k
JITTER FREQUENCY (Hz)
10k
100k
Figure 11. Minimum Input Jitter Tolerance of Receiver 13
CS61574A CS61575
In the Hardware Mode, data at RPOS and RNEG should be sampled on the rising edge of RCLK, the recovered clock. In the Extended Hardware Mode, data at RDATA should be sampled on the falling edge of RCLK. In the Host Mode, CLKE determines the clock polarity for which output data should be sampled as shown in Table 5.
MODE (pin 5) LOW (<0.2V) HIGH (>(V+) - 0.2V) HIGH (>(V+) - 0.2V) MIDDLE (2.5V) CLKE (pin 28) X LOW DATA RPOS RNEG RPOS RNEG SDO RPOS RNEG SDO RDATA CLOCK RCLK RCLK RCLK RCLK SCLK RCLK RCLK SCLK RCLK Clock Edge for Valid Data Rising Rising Rising Rising Falling Falling Falling Rising Falling
forced to its center frequency. Table 6 shows the status of RCLK upon LOS.
Crystal present? No Yes Yes ACLKI present? Yes No Yes Source of RCLK ACLKI Centered Crystal ACLKI via the Jitter Attenuator
Table 6. RCLK Status at LOS
Jitter Attenuator The jitter attenuator reduces wander and jitter in the recovered clock signal. It consists of a 32 or 192-bit FIFO, a crystal oscillator, a set of load capacitors for the crystal, and control logic. The jitter attenuator exceeds the jitter attenuation requirements of Publications 43802 and REC. G.742. A typical jitter attenuation curve is shown in Figure 12. The CS61575 fully meets AT&T 62411 jitter attenuation requirements. The CS61574A will have a discontinuity in the jitter transfer function when the incoming jitter amplitude exceeds approximately 23 UIs. The jitter attenuator works in the following manner. The recovered clock and data are input to the FIFO with the recovered clock controlling the FIFO's write pointer. The crystal oscillator controls the FIFO's read pointer which reads data out of the FIFO and presents it at RPOS and RNEG (or RDATA). RCLK is equivalent to the oscillator's output. By changing the load capacitance that the IC presents to the crystal, the oscillatior frequency (and RCLK) is adjusted to the average frequency of the recovered signal. Logic determines the phase relationship between the read and write pointers and decides how to adjust the load capacitance of the crystal. Jitter is absorbed in the FIFO according to the jitter transfer characteristic shown in Figure 12.
HIGH
X
X = Don't care Table 5. Data Output/Clock Relationship
Loss of Signal The receiver will indicate loss of signal after power-up, reset or upon receiving 175 consecutive zeros. A digital counter counts received zeros, based on RCLK cycles. A zero is received when the RTIP and RRING inputs are below the input comparator slicing threshold level established by the peak detector. After the signal is removed for a period of time the data slicing threshold level decays to approximately 300 mVpeak. If ACLKI is present during the LOS state, ACLKI is switched into the input of the jitter attenuator, resulting in RCLK matching the frequency of ACLKI. The jitter attenuator buffers any instantaneous changes in phase between the last recovered clock and the ACLKI reference clock. This means that RCLK will smoothly transition to the new frequency. If ACLKI is not present, then the crystal oscillator of the jitter attenuator is
14
DS154F2
CS61574A CS61575
0
a) Minimum Attenuation Limit
10
Attenuation in dB
20
30 40 50 60 1 10 100 b) Maximum Attenuation Limit
62411 Requirements
Measured Performance 1k 10 k
The CS61574A has a 32-bit FIFO which allows it to absorb jitter with minimum data delay in T1 and E1 switching or transmission applications. The CS61574A will tolerate large amplitude jitter by tracking rather than attenuating it, preventing data errors so that the jitter may be absorbed in external frame buffers. With large amplitude input jitter, the CS61574A jitter transfer function may exhibit some jitter peaking, but will offer performance comparable to the CS61574. The jitter attenuator may be bypassed by pulling XTALIN to RV+ through a 1 k resistor and providing a 1.544 MHz (or 2.048 MHz) clock on ACLKI. RCLK may exhibit quantization jitter of approximately 1/13 UIpp and a duty cycle of approximately 30% (70%) when the attenuator is disabled. Local Loopback Local loopback is selected by taking LLOOP, pin 27, high or by setting the LLOOP register bit via the serial interface. The local loopback mode takes clock and data presented on TCLK, TPOS, and TNEG (or TDATA), sends it through the jitter attenuator and outputs it at RCLK, RPOS and RNEG (or RDATA). If the jitter attenuator is disabled, it is bypassed. Inputs to the transmitter are still transmitted on TTIP and TRING, unless TAOS has been selected in which case, AMI-coded continuous ones are transmitted at the TCLK frequency. The receiver RTIP and RRING inputs are ignored when local loopback is in effect.
Frequency in Hz
Figure 12. Typical Jitter Transfer Function
The FIFO in the jitter attenuator is designed to prevent overflow and underflow. If the jitter amplitude becomes very large, the read and write pointers may get very close together. Should they attempt to cross, the oscillator's divide by four circuit adjusts by performing a divide by 3 1/2 or divide by 4 1/2 to prevent the overflow or underflow. During this activity, data will never be lost. The difference between the CS61575 and CS61574A is the depth of the FIFO in the jitter attenuator. The CS61575 has a 192-bit FIFO which allows it to attenuate large amplitude, low frequency jitter as required by AT&T 62411 (e.g., 28 UIpp @ 300 Hz). This makes the CS61575 ideal for use in T1 Customer Premises Equipment which must be compatible with AT&T 62411 requirements. In single-line Stratum 4, Type II systems which are loop-timed, he CS61575 recovered clock can be used as the transmit clock eliminating the need for an external system clock synchronizer. In Stratum 4, Type I systems which transfer timing and require a clock synchronizer, the CS61575 simplifies the design of the synchronizer by absorbing large amplitude low frequency jitter before it reaches the synchronizer.
DS154F2
15
CS61574A CS61575
Remote Loopback Remote loopback is selected by taking RLOOP, pin 26, high or by setting the RLOOP register bit via the serial interface. In remote loopback, the recovered clock and data input on RTIP and RRING are sent through the jitter attenuator and back out on the line via TTIP and TRING. Selecting remote loopback overrides any TAOS request (see Table 7). The recovered incoming signals are also sent to RCLK, RPOS and RNEG (or RDATA). Simultaneous selection of local and remote loopback modes is not valid (see Reset).
mally low, and goes high upon detecting a driver failure. The driver performance monitor consists of an activity detector that monitors the transmitted signal when MTIP is connected to TTIP and MRING is connected to TRING. DPM will go high if the absolute difference between MTIP and MRING does not transition above or below a threshold level within a time-out period. In the Host Mode, DPM is available from both the register and pin 11. Whenever more than one line interface IC resides on the same circuit board, the effectiveness of the driver performance monitor can be maximized by having each IC monitor performance of a neighboring IC, rather than having it monitor its own performance. Note that a CS61574A or CS61575 can not be used to monitor a CS61574 due to output stage differences. Line Code Encoder/Decoder In the Extended Hardware Mode, three line codes are available: AMI, B8ZS and HDB3. The input to the encoder is TDATA. The outputs from the decoder are RDATA and BPV (Bipolar Violation Strobe). The encoder and decoder are selected using the LEN2, LEN1, LEN0, TCODE and RCODE pins as shown in Table 8.
LEN 2/1/0 000 010-111 HDB3 B8ZS Encoder Encoder AMI Encoder HDB3 B8ZS Decoder Decoder AMI Decoder
RLOOP TAOS Input Input Signal Signal 0 0 1 0 1 X
Source of Data for TTIP & TRING TDATA all 1s
Source of Clock for TTIP & TRING TCLK TCLK
RTIP & RRING RTIP & RRING (RCLK)
Notes: 1. X = Don't care. The identified All Ones Select input is ignored when the indicated loopback is in effect. 2. Logic 1 indicates that Loopback or All Ones option is selected.
Table 7. Interaction of RLOOP with TAOS
In the Extended Hardware Mode the transmitted data is looped before the AMI/B8ZS/HDB3 encoder/decoder during remote loopback so that the transmitted signal matches the received signal, even in the presence of received bipolar violations. Data output on RDATA is decoded, however, if RCODE is low. Driver Performance Monitor To aid in early detection and easy isolation of non-functioning links, the IC is able to monitor transmit drive performance and report when the driver is no longer operational. This feature can be used to monitor either the device's performance or the performance of a neighboring driver. The driver performance monitor indicator is nor16
TCODE (Transmit Encoder Selection) RCODE (Receiver Decoder Selection)
LOW HIGH LOW HIGH
Table 8. Encoder/Decoder Selection DS154F2
CS61574A CS61575
Alarm Indication Signal In the Extended Hardware Mode, the receiver sets the output pin AIS high when less than 9 zeros are detected out of 8192 bit periods. AIS returns low when 9 or more zeros are detected out of 8192 bit periods. Parallel Chip Select In the Extended Hardware Mode, PCS can be used to gate the digital control inputs: TCODE, RCODE, LEN0, LEN1, LEN2, RLOOP, LLOOP and TAOS. Inputs are accepted on these pins only when PCS is low and will immediately change the operating state of the device. Therefore, when cycling PCS to update the operating state, the digital control inputs should be stable for the entire PCS low period. The digital control inputs are ignored when PCS is high. Power On Reset / Reset Upon power-up, the IC is held in a static state until the supply crosses a threshold of approximately 3 Volts. When this threshold is crossed, the device will delay for about 10 ms to allow the power supply to reach operating voltage. After this delay, calibration of the delay lines used in the transmit and receive sections commences. The delay lines can be calibrated only if a reference clock is present. The reference clock for the receiver is provided by the crystal oscillator, or ACLKI if the oscillator is disabled. The reference clock for the transmitter is provided by TCLK. The initial calibration should take less than 20 ms. In operation, the delay lines are continuously calibrated, making the performance of the device independent of power supply or temperature variations. The continuous calibration function forgoes any requirement to reset the line interface when in operation. However, a reset function is available which will clear all registers.
DS154F2
In the Hardware and Extended Hardware Modes, a reset request is made by simultaneously setting both the RLOOP and LLOOP pins high for at least 200 ns. Reset will initiate on the falling edge of the reset request (falling edge of RLOOP and LLOOP). In the Host Mode, a reset is initiated by simultaneously writing RLOOP and LLOOP to the register. In either mode, a reset will set all registers to 0 and force the oscillator to its center frequency before initiating calibration. A reset will also set LOS high. Serial Interface In the Host Mode, pins 23 through 28 serve as a microprocessor/microcontroller interface. One on-board register can be written to via the SDI pin or read from via the SDO pin at the clock rate determined by SCLK. Through this register, a host controller can be used to control operational characteristics and monitor device status. The serial port read/write timing is independent of the system transmit and receive timing. Data transfers are initiated by taking the chip select input, CS, low (CS must initially be high). Address and input data bits are clocked in on the rising edge of SCLK. The clock edge on which output data is stable and valid is determined by CLKE as shown in Table 5. Data transfers are terminated by setting CS high. CS may go high no sooner than 50 ns after the rising edge of the SCLK cycle corresponding to the last write bit. For a serial data read, CS may go high any time to terminate the output. Figure 13 shows the timing relationships for data transfers when CLKE = 1. When CLKE = 1, data bit D7 is held until the falling edge of the 16th clock cycle. When CLKE = 0, data bit D7 is held until the rising edge of the 17th clock cycle. SDO goes High-Z after CS goes high or at the end of the hold period of data bit D7.
17
CS61574A CS61575
CS SCLK SDI SDO
R/W
0
0
0
0
1
0
0
D0 D0
D1 D1
Address/Command Byte
D2 D3 D4 D5 Data Input/Output D2 D3 D4 D5
D6 D6
D7 D7
Figure 13. Input/Output Timing
An address/command byte, shown in Table 9, precedes a data register. The first bit of the address/command byte determines whether a read or a write is requested. The next six bits contain the address. The line interface responds to address 16 (0010000). The last bit is ignored.
LSB, first bit 0 1 2 3 4 5 6 7 R/W ADDP ADD1 ADD2 ADD3 ADD4 X Read/Write Select; 0 = write, 1 = read LSB of address, Must be 0 Must be 0 Must be 0 Must be 0 Must be 1 Reserved - Must be 0 Don't Care
Writing a "1" to either "Clear LOS" or "Clear DPM" over the serial interface has three effects: 1) The current interrupt on the serial interface will be cleared. (Note that simply reading the register bits will not clear the interrupt). 2) Output data bits 5, 6 and 7 will be reset as appropriate. 3) Future interrupts for the corresponding LOS or DPM will be prevented from occurring. Writing a "0" to either "Clear LOS" or "Clear DPM" enables the corresponding interrupt for LOS or DPM. Output data from the serial interface is presented as shown in Tables 11 and 12. Bits 2, 3 and 4 can be read to verify line length selection. Bits 5, 6 and 7 must be decoded. Codes 101, 110 and 111 (Bits 5, 6 and 7) indicate intermittent loss of signal and/or driver problems. SDO goes to a high impedance state when not in use. SDO and SDI may be tied together in applications where the host processor has a bi-directional I/O port.
MSB, last bit
Table 9. Address/Command Byte
The data register, shown in Table 10, can be written to the serial port. Data is input on the eight clock cycles immediately following the address/command byte. Bits 0 and 1 are used to clear an interrupt issued from the INT pin, which occurs in response to a loss of signal or a problem with the output driver.
LSB, first bit in
MSB, last bit in
0 1 2 3 4 5 6 7
clr LOS clr DPM LEN0 LEN1 LEN2 RLOOP LLOOP TAOS
Clear Loss Of Signal Clear Driver Performance Bit 0 - Line Length Select Bit 1 - Line Length Select Bit 2 - Line Length Select Remote Loopback Local Loopback Transmit All Ones Select
LSB, first bit in
0 1 2 3 4
LOS DPM LEN0 LEN1 LEN2
Loss Of Signal Driver Performance Bit 0 - Line Length Select Bit 1 - Line Length Select Bit 2 - Line Length Select
Table 10. Input Data Register 18
Table 11. Output Data Bits 0 - 4 DS154F2
CS61574A CS61575
Bits 6 0 0 1 1 0 0 1 1 Status 7 0 1 0 1 0 1 0 1 Reset has occurred or no program input. TAOS in effect. LLOOP in effect TAOS/LLOOP in effect. RLOOP in effect. DPM changed state since last "clear DPM" occurred. LOS changed state since last "clear LOS" occurred. LOS and DPM have changed state since last "clear LOS" and "clear DPM".
5 0 0 0 0 1 1 1 1
Schematic & Layout Review Service
Confirm Optimum Schematic & Layout Before Building Your Board. For Our Free Review Service Call Applications Engineering.
Call: (512) 445-7222
Table 12. Coding for Serial Output bits 5,6,7
Power Supply The device operates from a single +5 Volt supply. Separate pins for transmit and receive supplies provide internal isolation. These pins should be connected externally near the device and decoupled to their respective grounds. TV+ must not exceed RV+ by more than 0.3V. Decoupling and filtering of the power supplies is crucial for the proper operation of the analog circuits in both the transmit and receive paths. A 1.0 F capacitor should be connected between TV+ and TGND, and a 0.1 F capacitor should be connected between RV+ and RGND. Use mylar or ceramic capacitors and place them as closely as possible to their respective power supply pins. A 68 F tantalum capacitor should be added close to the RV+/RGND supply. Wire-wrap breadboarding of the line interface is not recommended because lead resistance and inductance serve to defeat the function of the decoupling capacitors.
DS154F2
19
CS61574A CS61575
PIN DESCRIPTIONS Hardware Mode
ACLKI TCLK TPOS TNEG MODE RNEG RPOS RCLK XTALIN XTALOUT DPM LOS TTIP TGND
1
2
28
27
3
4 5
26
25 24
6
7 8
23
22 21
9
10
20
19
11
12 13
18
17 16
14
15
TAOS LLOOP RLOOP LEN2 LEN1 LEN0 RGND RV+ RRING RTIP MRING MTIP TRING TV+
ACLKI TCLK TPOS TNEG MODE RNEG RPOS RCLK XTALIN XTALOUT DPM LOS TTIP TGND
5 4 3 2 1 28 27 26 25
TAOS LLOOP RLOOP LEN2 LEN1 LEN0 RGND RV+ RRING RTIP MRING MTIP TRING TV+
6
7 top view
24
23 22
8
9 10
21
20
11
12 13 14 15 16 17 18
19
20
DS154F2
CS61574A CS61575
Extended Hardware Mode
ACLKI TCLK TDATA TCODE MODE BPV RDATA RCLK XTALIN XTALOUT AIS LOS TTIP TGND
1
2
28
27
3
4 5
26
25 24
6
7 8
23
22 21
9
10
20
19
11
12 13
18
17 16
14
15
TAOS LLOOP RLOOP LEN2 LEN1 LEN0 RGND RV+ RRING RTIP PCS RCODE TRING TV+
ACLKI TCLK TDATA TCODE MODE BPV RDATA RCLK XTALIN XTALOUT AIS LOS TTIP TGND
5 4 3 2 1 28 27 26 25
TAOS LLOOP RLOOP LEN2 LEN1 LEN0 RGND RV+ RRING RTIP PCS RCODE TRING TV+
6
7 top view
24
23 22
8
9 10
21
20
11
12 13 14 15 16 17 18
19
DS154F2
21
CS61574A CS61575
Host Mode
ACLKI TCLK TPOS TNEG MODE RNEG RPOS RCLK XTALIN XTALOUT DPM LOS TTIP TGND
1
2
28
27
3
4 5
26
25 24
6
7 8
23
22 21
9
10
20
19
11
12 13
18
17 16
14
15
CLKE SCLK CS SDO SDI INT RGND RV+ RRING RTIP MRING MTIP TRING TV+
ACLKI TCLK TPOS TNEG MODE RNEG RPOS RCLK XTALIN XTALOUT DPM LOS TTIP TGND
5 4 3 2 1 28 27 26 25
CLKE SCLK CS SDO SDI INT RGND RV+ RRING RTIP MRING MTIP TRING TV+
6
7 top view
24
23 22
8
9 10
21
20
11
12 13 14 15 16 17 18
19
22
DS154F2
CS61574A CS61575
Power Supplies RGND - Ground, Pin 22. Power supply ground for all subcircuits except the transmit driver; typically 0 Volts. RV+ - Power Supply, Pin 21. Power supply for all subcircuits except the transmit driver; typically +5 Volts. TGND - Ground, Transmit Driver, Pin 14. Power supply ground for the transmit driver; typically 0 Volts. TV+ - Power Supply, Transmit Driver, Pin 15. Power supply for the transmit driver; typically +5 Volts. TV+ must not exceed RV+ by more than 0.3 V. Oscillator XTALIN, XTALOUT - Crystal Connections, Pins 9 and 10. A 6.176 MHz (or 8.192 MHz) crystal should be connected across these pins. If a 1.544 MHz (or 2.048 MHz) clock is provided on ACLKI (pin 1), the jitter attenuator may be disabled by tying XTALIN, Pin 9 to RV+ through a 1 k resistor, and floating XTALOUT, Pin 10. Overdriving the oscillator with an external clock is not supported. Control ACLKI - Alternate External Clock Input, Pin 1. A 1.544 MHz (or 2.048 MHz) clock may be input to ACLKI, or this pin must be tied to ground. During LOS, the ACLKI input signal, if present, is output on RCLK through the jitter attenuator. CLKE - Clock Edge, Pin 28. (Host Mode) Setting CLKE to logic 1 causes RPOS and RNEG to be valid on the falling edge of RCLK, and SDO to be valid on the rising edge of SCLK. Conversely, setting CLKE to logic 0 causes RPOS and RNEG to be valid on the rising edge of RCLK, and SDO to be valid on the falling edge of SCLK. CS - Chip Select, Pin 26. (Host Mode) This pin must transition from high to low to read or write the serial port. INT - Receive Alarm Interrupt, Pin 23. (Host Mode) Goes low when LOS or DPM change state to flag the host processor. INT is cleared by writing "clear LOS" or "clear DPM" to the register. INT is an open drain output and should be tied to the power supply through a resistor.
DS154F2
23
CS61574A CS61575
LEN0, LEN1, LEN2 - Line Length Selection, Pins 23, 24 and 25. (Hardware and Extended Hardware Modes) Determines the shape and amplitude of the transmitted pulse to accommodate several cable types and lengths. See Table 3 for information on line length selection. Also controls the receiver slicing level and the line code in Extended Hardware Mode. LLOOP - Local Loopback, Pin 27. (Hardware and Extended Hardware Modes) Setting LLOOP to a logic 1 routes the transmit clock and data through the jitter attenuator to the receive clock and data pins. TCLK and TPOS/TNEG (or TDATA) are still transmitted unless overridden by a TAOS request. Inputs on RTIP and RRING are ignored. MODE - Mode Select, Pin 5. Driving the MODE pin high puts the line interface in the Host Mode. In the host mode, a serial control port is used to control the line interface and determine its status. Grounding the MODE pin puts the line interface in the Hardware Mode, where configuration and status are controlled by discrete pins. Floating the MODE pin or driving it to +2.5 Vselects the Extended Hardware Mode, where configuration and status are controlled by discrete pins. When floating MODE, there should be no external load on the pin. MODE defines the status of 13 pins (see Table 2). PCS - Parallel Chip Select, Pin 18. (Extended Hardware Mode) Setting PCS high causes the line interface to ignore the TCODE, RCODE, LEN0, LEN1, LEN2, RLOOP, LLOOP and TAOS inputs. RCODE - Receiver Decoder Select, Pin 17. (Extended Hardware Mode) Setting RCODE low enables B8ZS or HDB3 zero substitution in the receiver decoder. Setting RCODE high enables the AMI receiver decoder (see Table 8). RLOOP - Remote Loopback, Pin 26. (Hardware and Extended Hardware Modes) Setting RLOOP to a logic 1 causes the recovered clock and data to be sent through the jitter attenuator (if active) and through the driver back to the line. The recovered signal is also sent to RCLK and RPOS/RNEG (or RDATA). Any TAOS request is ignored. Simultaneously taking RLOOP and LLOOP high for at least 200 ns initiates a device reset. SCLK - Serial Clock, Pin 27. (Host Mode) Clock used to read or write the serial port registers. SCLK can be either high or low when the line interface is selected using the CS pin. SDI - Serial Data Input, Pin 24. (Host Mode) Data for the on-chip register. Sampled on the rising edge of SCLK. SDO - Serial Data Output, Pin 25. (Host Mode) Status and control information from the on-chip register. If CLKE is high SDO is valid on the rising edge of SCLK. If CLKE is low SDO is valid on the falling edge of SCLK. This pin goes to a high-impedance state when the serial port is being written to or after bit D7 is output.
24
DS154F2
CS61574A CS61575
TAOS - Transmit All Ones Select, Pin 28. (Hardware and Extended Hardware Modes) Setting TAOS to a logic 1 causes continuous ones to be transmitted at the frequency determined by TCLK. TCODE - Transmitter Encoder Select, Pin 4. (Extended Hardware Mode) Setting TCODE low enables B8ZS or HDB3 zero substitution in the transmitter encoder. Setting TCODE high enables the AMI transmitter encoder . Data RCLK - Recovered Clock, Pin 8. The receiver recovered clock generated by the jitter attenuator is output on this pin.When in the loss of signal state ACLKI (if present) is output on RCLK via the jitter attenuator. If ACLKI is not present during LOS, RCLK is forced to the center frequency of the crystal oscillator.. RDATA - Receive Data - Pin 7. (Extended Hardware Mode) Data recovered from the RTIP and RRING inputs is output at this pin, after being decoded by the line code decoder. RDATA is NRZ. RDATA is stable and valid on the falling edge of RCLK. RPOS, RNEG - Receive Positive Data, Receive Negative Data, Pins 6 and 7. (Hardware and Host Modes) The receiver recovered NRZ digital data is output on these pins. In the Hardware Mode, RPOS and RNEG are stable and valid on the rising edge of RCLK. In the Host Mode, CLKE determines the clock edge for which RPOS and RNEG are stable and valid. See Table 5. A positive pulse (with respect to ground) received on the RTIP pin generates a logic 1 on RPOS, and a positive pulse received on the RRING pin generates a logic 1 on RNEG. RTIP, RRING - Receive Tip, Receive Ring, Pins 19 and 20. The AMI receive signal is input to these pins. A center-tapped, center-grounded, 2:1, step-up transformer is required on these inputs, as shown in Figure A1 in the Applications section. Data and clock are recovered and output on RCLK and RPOS/RNEG or RDATA. TCLK - Transmit Clock, Pin 2. The1.544 MHz (or 2.048 MHz) transmit clock is input on this pin. TPOS/TNEG or TDATA are sampled on the falling edge of TCLK. TDATA - Transmit Data, Pin 3. (Extended Hardware Mode) Transmitter NRZ input data which passes through the line code encoder, and is then driven on to the line through TTIP and TRING. TDATA is sampled on the falling edge of TCLK. TPOS, TNEG - Transmit Positive Data, Transmit Negative Data, Pins 3 and 4. (Hardware and Host Modes) Inputs for clock and data to be transmitted. The signal is driven on to the line through TTIP and TRING. TPOS and TNEG are sampled on the falling edge of TCLK. A TPOS input causes a positive pulse to be transmitted, while a TNEG input causes a negative pulse to be transmitted.
DS154F2
25
CS61574A CS61575
TTIP, TRING - Transmit Tip, Transmit Ring, Pins 13 and 16. The AMI signal is driven to the line through these pins. The transmitter output is designed to drive a 75 load between TTIP and TRING. A transformer is required as shown in Table A1. Status AIS - Alarm Indication Signal, Pin 11. (Extended Hardware Mode) AIS goes high when unframed all-ones condition (blue alarm) is detected, using the detection criteria of less than three zeros out of 2048 bit periods. BPV- Bipolar Violation Strobe, Pin 6. (Extended Hardware Mode) BPV strobes high when a bipolar violation is detected in the received signal. B8ZS (or HDB3) zero substitutions are not flagged as bipolar violations if the B8ZS (or HDB3) decoder has been enabled. DPM - Driver Performance Monitor, Pin 11. (Hardware and Host Modes) DPM goes high if no activity is detected on MTIP and MRING. LOS - Loss of Signal, Pin 12. LOS goes high when 175 consecutive zeros have been received. LOS returns low when the ones density reaches 12.5% (based upon 175 bit periods starting with a one and containing less than 100 consectutive zeros) as prescribed in ANSI T1.231-1993. When in the loss of signal state RPOS/RNEG or RDATA are forced low, and ACLKI (if present) is output on RCLK via the jitter attenuator. If ACLKI is not present during LOS, RCLK is forced to the center frequency of the crystal oscillator. MTIP, MRING - Monitor Tip, Monitor Ring, Pins 17 and 18. (Hardware and Host Modes) These pins are normally connected to TTIP and TRING and monitor the output of a line interface IC. If the INT pin in the host mode is used, and the monitor is not used, writing "clear DPM" to the serial interface will prevent an interrupt from the driver performance monitor.
Ordering Guide
Model CS61575-IP1 CS61575-IL1 CS61574A-IP1 CS61574A-IL1 Frequency T1 & E1 T1 & E1 T1 & E1 T1 & E1 FIFO Depth (Bits) 192 192 32 32 Package 28-pin Plastic DIP 28-pin PLCC 28-pin Plastic DIP 28-pin PLCC
26
DS154F2
CS61574A CS61575
28
15 E1
1
14
28 pin Plastic DIP
D A A1
e1
SEATING PLANE
B1
L
B
C eA
NOTES: 1. POSITIONAL TOLERANCE OF LEADS SHALL BE WITHIN 0.25mm (0.010") AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION eA TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION E1 DOES NOT INCLUDE MOLD FLASH.
MILLIMETERS INCHES DIM MIN NOM MAX MIN NOM MAX 3.94 4.32 5.08 0.155 0.170 0.200 A A1 0.51 0.76 1.02 0.020 0.030 0.040 0.36 0.46 0.56 0.014 0.018 0.022 B B1 1.02 1.27 1.65 0.040 0.050 0.065 0.20 0.25 0.38 0.008 0.010 0.015 C 36.45 36.83 37.21 1.435 1.450 1.465 D E1 13.72 13.97 14.22 0.540 0.550 0.560 e1 2.41 2.54 2.67 0.095 0.100 0.105 eA 15.24 15.87 0.600 0.625 L 3.18 0.150 3.81 0.125 0 15 15 0
28-pin PLCC
28
E1 E
MILLIMETERS INCHES
DIM
MIN NOM MAX
4.20 4.45
MIN NOM MAX
A A1
B
4.57 0.165 0.175 0.180
2.29 0.33
2.79 0.41
3.04 0.090 0.110 0.120 0.53 0.013 0.016 0.021
D/E 12.32 12.45 12.57 0.485 0.490 0.495
D1 D
D1/E1 11.43 11.51 11.58 0.450 0.453 0.456
D2/E2 9.91 10.41 10.92 0.390 0.410 0.430
e
1.19
1.27
1.35 0.047 0.050 0.053
B
e A1 D2/E2 A
DS154F2
27
CS61574A CS61575
APPLICATIONS
+5V + 68 F RGND 28 Control & Monitor 1 12 11 RV+ 5 7 6 Frame Format Encoder/ Decoder 8 3 4 2 9 XTL 10 CLKE ACLKI
LOS
0.1 F 21 RV+ 15 TV+
+
1.0 F TGND
+5V 100 k
SCLK CS
INT
27 26 23 24 25 P Serial Port
DPM
SDI SDO
MODE RPOS RNEG RCLK
TPOS
CS61574A OR CS61575 IN HOST MODE
RTIP
19 R1 20 17 18 16 13 R2
1 2 3 5 2CT:1 PE-65351 0.47 F 2 6 RECEIVE 6 LINE
RRING
MTIP
TNEG TCLK
XTALIN XTALOUT RGND 22
MRING TRING
TGND 14 TTIP
1 TRANSMIT 5 LINE
1:1.15 PE-65388
Figure A1. T1 Host Mode Configuration Frequency MHz 1.544 (T1) 2.048 (E1) Cable 100 120 75 R1 and R2 Transmit Transformer 200 1:1.15 240 1:1.26 150 1:1 Crystal XTL CXT6176 CXT8192
Table A1. External Component Values
Line Interface Figures A1-A3 show typical T1 and E1 line interface application circuits. Table A1 shows the external components which are specific to each application. Figure A1 illustrates a T1 interface in the Host Mode. Figure A2 illustrates a 120 E1 interface in the Hardware Mode. Figure A3 illustrates a 75 E1 interface in the Extended Hardware Mode The receiver transformer has a grounded center tap on the IC side. Resistors between the RTIP
28
and RRING pins to ground provide the termination for the receive line. The transmitter transformer matches the 75 transmitter output impedance to the line impedance. Figures A1-A3 show a 0.47 F capacitor in series with the transmit transformer primary. This capacitor is needed to prevent any output stage imbalance from resulting in a DC current through the transformer primary. This current might saturate the transformer producing an output offset level shift.
DS154F2
CS61574A CS61575
+5V + 68 F RGND 28 1 Control & Monitor 26 27 12 11 5 7 6 Frame Format Encoder/ Decoder 8 3 4 2 9 XTL 10 TAOS ACLKI RLOOP LLOOP LOS DPM MODE RPOS RNEG RCLK TPOS TNEG TCLK XTALIN XTALOUT RGND 22 TGND 14 LEN0 LEN1 LEN2 23 24 25 Line Length Setting 0.1 F 21 RV+ 15 TV+ + 1.0 F TGND
CS61574A OR CS61575 IN HARDWARE MODE
RTIP
19 R1 20 R2
1 2 3 5 2CT:1 PE-65351 0.47 F 2 6 RECEIVE 6 LINE
RRING
MTIP
17 18 16 13
MRING TRING TTIP
1 TRANSMIT 5 LINE
1:1.26 PE-65389
Figure A2. 120 , E1 Hardware Mode Configuration
+5V + 68 F RGND 17 18 6 28 Control & Monitor 1 26 27 12 11 5 4 7 Frame Format Encoder/ Decoder 8 3 2 9 XTL 10 RCODE PCS BPV TAOS ACLKI RLOOP LLOOP LOS AIS MODE TCODE RDATA RCLK TDATA TCLK XTALIN XTALOUT RGND 22 TGND 14 TRING TTIP 16 13 LEN0 LEN1 LEN2 23 24 25 Line Length Setting 0.1 F 21 RV+ 15 TV+ + 1.0 F TGND
CS61574A OR CS61575 IN EXTENDED HARDWARE MODE
RTIP
19 R1 20 R2
1 2 3 5 2CT:1 PE-65351
0.47 F 2
RECEIVE 6 LINE
RRING
3 TRANSMIT 5 LINE
6
1:1 PE-65389
Figure A3. 75 , E1 Extended Hardware Mode Configuration DS154F2 29
CS61574A CS61575
Parameter Turns Ratio
Receiver 1:2 CT 5%
Transmitter 1:1 1.5 % for 75 E1 1:1.15 5 % for 100 T1 1:1.26 1.5 % for 120 E1 1.5 mH min. @ 772 kHz 0.3 H max. @ 772 kHz 0.4 H max. @ 772 kHz 18 pF max. 16 V-s min. for T1 12 V-s min. for E1
Primary Inductance Primary Leakage Inductance Secondary Leakage Inductance Interwinding Capacitance ET-constant
600 H min. @ 772 kHz 1.3 H max. @ 772 kHz 0.4 H max. @ 772 kHz 23 pF max. 16 V-s min. for T1 12 V-s min. for E1
Table A2. Transformer Specifications
Transformers Recommended transmitter and receiver transformer specifications are shown in Table A2. The transformers in Table A3 have been tested and recommended for use with the CS61574A and CS61575. Refer to the "Telecom Transformer Selection Guide" for detailed schematics which show how to connect the line interface IC with a particular transformer. In applications where it is advantageous to use a single transmitter transformer for 75 and 120 E1 applications, a 1:1.26 transformer may be used. Although transmitter return loss will be reduced for 75 applications, the pulse amplitude will be correct across a 75 load. Selecting an Oscillator Crystal Specific crystal parameters are required for proper operation of the jitter attenuator. It is recommended that the Crystal Semiconductor CXT6176 crystal be used for T1 applications and the CXT8192 crystal be used for E1 applications.
Designing for AT&T 62411 For additional information on the requirements of AT&T 62411 and the design of an appropriate system synchronizer, please refer to the Crystal Semiconductor Application Notes: "AT&T 62411 Design Considerations - Jitter and Synchronization" and "Jitter Testing Procedures for Compliance with AT&T 62411". Transmit Side Jitter Attenuation In some applications it is desirable to attenuate jitter from the signal to be transmitted. A CS61575 in local loopback mode can be used as a jitter attenuator. The inputs to the jitter attenuator are TPOS, TNEG, TCLK. The outputs from the jitter attenuator are RPOS, RNEG and RCLK. Line Protection Secondary protection components can be added to provide lightning surge and AC power-cross immunity. Refer to the application note "Secondary Line Protection for T1 and E1 Line Cards" for detailed information on the different electrical safety standards and specific application circuit recommendations.
30
DS154F2
CS61574A CS61575
Application RX: T1 & E1 TX: T1 TX: E1 (75 & 120 ) RX &TX: T1 RX &TX: E1 (75 & 120 ) RX &TX: T1 RX &TX: E1 (75 & 120 ) RX : T1 & E1 TX: E1 (75 & 120 )
Turns Ratio(s) 1:2CT
Manufacturer Pulse Engineering Schott Bel Fuse Pulse Engineering Schott Bel Fuse Pulse Engineering Schott Bel Fuse Pulse Engineering Bel Fuse Pulse Engineering Bel Fuse Pulse Engineering Bel Fuse Pulse Engineering Bel Fuse Pulse Engineering Pulse Engineering
Part Number PE-65351 67129300 0553-0013-HC PE-65388 67129310 0553-0013-RC PE-65389 67129320 0553-0013-SC PE-65565 0553-0013-7J PE-65566 0553-0013-8J PE-65765 S553-0013-06 PE-65766 S553-0013-07 PE-65835 PE-65839
Package Type 1.5 kV through-hole, single
1:1.15
1.5 kV through-hole, single
1:1.26 1:1 1:2CT 1:1.15 1:2CT 1:1.26 1:1 1:2CT 1:1.15 1:2CT 1:1.26 1:1 1:2CT 1:1.26 1:1
1.5 kV through-hole, single
1.5 kV through-hole, dual 1.5 kV through-hole, dual
1.5 kVsurface-mount, dual 1.5 kV surface-mount, dual
3 kV through-hole, single EN60950, EN41003 approved 3 kV through-hole, single EN60950, EN41003 approved
Table A3. Recommended Transformers
Interfacing The CS61575 and CS61574A With the CS62180B T1 Transceiver To interface with the CS62180B, connect the devices as shown in Figure A4. In this case, the line interface and CS62180B are in Host Mode controlled by a microprocessor serial interface. If the line interface is used in Hardware Mode, then the line interface RCLK output must be inverted before being input to the CS62180B. If the CS61575 or CS61574A is used in Extended Hardware Mode, the RCLK output does not have to be inverted before being input to the CS62180B.
TO HOST CONTROLLER
SCLK SDO SDI CS
TCLK TPOS TNEG
1.544 MHz CLOCK SIGNAL
ACLK TCLK TPOS TNEG
SCLK SDO SDI CS INT 22k V+ 100k V+
RNEG RPOS RCLK
RNEG RPOS RCLK
CLKE MODE
CS62180B
CS61574A OR CS61575
Figure A4. Interfacing the CS61574A or CS61575 with a CS62180B (Host Mode)
DS154F2
31
* Notes *
CDB61534, CDB61535, CDB61535A, CDB6158, CDB6158A, CDB61574, CDB61574A, CDB61575, CDB61577, CDB615304A, & CDB61305A
Line Interface Evaluation Board
Features General Description
The evaluation board includes a socketed line interface device and all support components necessary for evaluation. The board is powered by an external 5 Volt supply. The board may be configured for 100 twisted-pair T1, 75 coax E1, or 120 twisted-pair E1 operation. Binding posts are provided for line connections. Several BNC connectors are available to provide system clocks and data I/O. Two LED indicators monitor device alarm conditions. The board supports all line interface operating modes. ORDERING INFORMATION: CDB61534, CDB61535. CDB61535A, CDB6158, CDB6158A, CDB61574, CDB61574A, CDB61575, CDB61577, CDB61304A, CDB61305A
+5V 0V
* * All Required Components for Complete
Socketed Line Interface Device Line Interface Evaluation Interface
* Configuration by DIP Switch or Serial * LED Status Indicators for Alarm
Conditions
* Support for Host, Hardware, and
Extended Hardware Modes
Mode Select Circuit Reset Circuit
Serial Interface Control Circuit
TTIP
TRING
Hardware Control Circuit LED Status Indicators ACLKI TCLK TPOS (TDATA)
TNEG (TCODE)
CS61534, CS61535, CS61535A, CS6158, CS6158A, CS61574, CS61574A, CS61575, CS61577, CS61304A or CS61305A
XTL
RTIP
RRING
RCLK
RPOS (RDATA)
RNEG (BPV)
Crystal Semiconductor Corporation P.O. Box 17847, Austin, TX 78760 (512) 445-7222 FAX: (512) 445-7581
SEP '95 DS40DB3 33
LINE INTERFACE EVALUATION BOARD
POWER SUPPLY As shown on the evaluation board schematic in Figure 1, power is supplied to the evaluation board from an external +5 Volt supply connected to the two binding posts labeled +5V and GND. Transient suppressor D10 protects the components on the board from over-voltage damage and reversed supply connections. The recommended power supply decoupling is provided by C1, C2 and C3. Ceramic capacitor C1 and electrolytic capacitor C2 are used to decouple RV+ to RGND. Capacitor C3 decouples TV+ to TGND. The TV+ and RV+ power supply traces are connected at the device socket U1. A ground plane on the component side of the evaluation board insures optimum performance. BOARD CONFIGURATION Pins on line interface device U1 with more than one pin name have different functions depending on the operating mode selected. Pin names not enclosed in parenthesis or square brackets describe the Hardware mode pin function. Pin names enclosed in parenthesis describe the Extended Hardware mode pin function. Pin names enclosed in square brackets describe the Host mode pin function.
Table 1 explains how to configure the evaluation board jumpers depending on the device installed and the desired operating mode. Mode selection is accomplished with slide switch SW1 and jumpers JP2, JP6, and JP7. The CS61535A, CS61574A, CS61575, CS61577, CS61304A, and CS61305A support the Hardware, Extended Hardware, and Host operating modes. The CS61534, CS61535, and CS61574 support the Hardware and Host operating modes. The CS6158 and CS6158A only support the Hardware operating mode. Hardware Mode In the Hardware operating mode, the line interface is configured using DIP switch S2. The digital control inputs to the device selected by S2 include: transmit all ones (TAOS), local loopback (LLOOP), remote loopback (RLOOP), and transmit line length selection (LEN2,LEN1,LEN0). Closing a DIP switch on S2 towards the label sets the device control pin of the same name to logic 1 (+5 Volts). Note that S2 switch positions TCODE and RCODE have no function in Hardware mode. In addition, the host processor interface connector JP1 should not be used in the Hardware mode. Two LED status indicators are provided in Hardware mode. The LED labeled DPM (AIS) illuminates when the line interface asserts the Driver
JUMPER JP1 JP2, JP6, JP7 JP3 JP4 JP5 JP8
POSITION A-A B-B IN OUT C-C D-D E-E F-F IN OUT
FUNCTION SELECTED Connector for external processor in Host operating mode. Extended Hardware operating mode. Hardware or Host operating modes. Hardware or Extended Hardware operating modes. Host operating mode. Connects the ACLKI BNC input to pin 1 of device. Grounds the ACLKI BNC input through 51 resistor R1. Transmit line connection for all applications except those listed for "F-F" on the next line. 75 coax E1 applications using the Schott 12932/12532 or PE-65389/65566 at transformer T1. Shorts resistor R2 for all applications except those listed for "OUT" on the next line. Inserts resistor R2 for 75 coax E1 applications using the CS61534, 35, 58, 74, or 77.
Table 1. Evaluation Board Jumper Settings
34
DS40DB3
LINE INTERFACE EVALUATION BOARD
RV+ +5V D10 P6KE GND (0V) C2 0.1F C3 1 F 15 TV+ Pin 6 RNEG (BPV) RCLK TCLK TCLK TPOS (TDATA) RPOS (RDATA) RV+ R15 100 S2 RCODE TCODE LEN0/INT LEN1/SDI LEN2/SD0 RLOOP/CS LLOOP/SCLK TAOS/CLKE INT SDI SDO CS SCLK
JP1 D9 1N914 Pin 3 C1 68F +
RV+
Prototyping Area
RV+ 14 TGND 22 RGND 21 RV+ 9 E1: CXT8192 T1: CXT6176 (not included for CS6158/58A) RTIP 19 R10 200 Change R9 and R10 for E1 operation T2 (see Table 2) 2:1 RTIP R13 (only included for CS6158/58A) 1k
6 RNEG (BPV) 8 RCLK 2 TCLK 3 TPOS (TDATA) 7 RPOS (RDATA)
RCLK
XTALIN {CS6158/58A: RT} XTALOUT {CS6158/58A: NC} RTIP
10
Pin 7 ACLKI R1 51.1 D JP4 D
ACLKI TNEG B A JP2
1 C B A C Pin 4 4
U1
ACLKI TNEG (TCODE) RRING
TTIP MRING (PCS)
RRING
R9 200 RRING
20 13 18 TTIP Pin 18 B
JP6
B
A
23 LEN0 [INT] 24 LEN1 [SDI] 25 LEN2 [SD0] 26 RLOOP [CS] 27 LLOOP [SCLK] 28 TAOS [CKLE]
TRING A TRING
MTIP (RCODE)
0.47 F C5
E
JP5
TTIP
E
16 Pin 17 17 B
A JP7
B
A
JP8
FF T1 (see Table 2) TRING
R2 4.4
LOS
MODE DPM (AIS)
5 R14 4.7k SIP C4 0.047F
MODE
11 DPM RV+ (AIS)
12 RV+ LOS Q1 2N2222 LED D3
R6 470
D8
(Used only for E1 75 applications with the CS61534, CS61535, CS6158, CS61574, OR CS61577)
S1 RESET R4 221k
Q2 2N2222 LED D2
R5 470
6
3
MODE SW1 8 7 RV+ 5 R16 1k 1 2 4 HOST:3-1,6-8 EXT HW: 3-2, 6-7 HW: 3-4, 6-5
U1: CS61534, CS61535, CS61535A, CS6158, CS6158A, CS61574, CS61574A, CS61575, CS61577, CS61304A, OR CS61305A
R18 R17 10k 10k
Figure 1. Evaluation Board Schematic
DS40DB3
35
LINE INTERFACE EVALUATION BOARD
Performance Monitor alarm. The LED labeled LOS illuminates when the line interface receiver has detected a loss of signal. Extended Hardware Mode In the Extended Hardware operating mode, the line interface is configured using DIP switch S2. The digital control inputs to the device selected by S2 include: transmit all ones (TAOS), local loopback (LLOOP), remote loopback (RLOOP), transmit line length selection (LEN2, LEN1, LEN0), transmit line code (TCODE), and receive line code (RCODE). Closing a DIP switch (moving it towards the S2 label) sets the device control pin of the same name to logic 1 (+5 Volts). Note that the TCODE and RCODE options are active low and are enabled when the switch is moved away from the S2 label. The parallel chip select input PCS is tied to ground in Extended Hardware mode to enable the device to be reconfigured when S2 is changed. In addition, the host processor interface connector JP1 should not be used in Extended Hardware mode. Two LED status indicators are provided in Extended Hardware mode. The LED labeled DPM (AIS) illuminates when the line interface detects the receive blue alarm (AIS). The LED labeled LOS illuminates when the line interface receiver has detected a loss of signal. Host Mode In the Host operating mode, the line interface is configured using a host processor connected to the serial interface port JP1. The S2 switch position labeled CLKE selects the active edge of SCLK and RCLK. Closing the CLKE switch selects RPOS and RNEG to be valid on the falling edge of RCLK and SDO to be valid on the rising edge of SCLK as required by the CS2180B T1 framer. All other DIP switch positions on S2 should be open (logic 0) to prevent shorting of the serial in36
terface signals. Resistor R15 is a current limiting resistor that prevents the serial interface signals from being shorted directly to the +5 Volt supply if any S2 switch, other than CLKE, is closed. Jumper JP3 should be out so the INT pin may be externally pulled-up at the host processor interrupt pin. Two LED status indicators are provided in Host mode. The LED labeled DPM (AIS) illuminates when the line interface asserts the Driver Performance Monitor alarm. The LED labeled LOS illuminates when the line interface receiver has detected a loss of signal. Manual Reset A manual reset circuit is provided that can be used in Hardware and Extended Hardware modes. The reset circuit consists of S1, R4, R16, C4, D8, and D9. Pressing switch S1 forces both LLOOP and RLOOP to a logic 1 and causes a reset. A reset is only necessary for the CS61534 device to calibrate the center frequency of the receiver clock recovery circuit. All other line interface units use a continuously calibrated clock recovery circuit that eliminates the reset requirement. TRANSMIT CIRCUIT The transmit clock and data signals are supplied on BNC inputs labeled TCLK, TPOS(TDATA), and TNEG. In the Hardware and Host operating modes, data is supplied on the TPOS(TDATA) and TNEG connectors in dual NRZ format. In the Extended Hardware operating mode, data is supplied in NRZ format on the TPOS(TDATA) connector and TNEG is not used. The transmitter output is transformer coupled to the line through a transformer denoted as T1 in Figure 1. The signal is available at the TTIP and TRING binding posts. Capacitor C5 is the recommended 0.47 F DC blocking capacitor.
DS40DB3
LINE INTERFACE EVALUATION BOARD
The evaluation board supports 100 twisted-pair T1, 75 coax E1, and 120 twisted-pair E1 operation. The CDB61534, CDB61535, CDB6158, CDB61574, and CDB61577 are supplied from the factory with a 1:2 transmit transformer that may be used for all T1 and E1 applications. The CDB61535A, CDB6158A, CDB61574A, CDB61575, CDB61304A, and CDB61305A are supplied with a 1:1.15 transmit transformer installed for T1 applications. An additional 1:1:1.26 transformer for E1 applications is provided with the board. This transformer requires JP5 to be jumpered across F-F for 75 coax E1 applications. The CDB61534, CDB61535, CDB6158, CDB61574, and CDB61577 require the JP8 jumper to be out for 75 coax E1 applications. This inserts resistor R2 to reduce the transmit pulse amplitude and meet the 2.37 V nominal pulse amplitude requirement in CCITT G.703. In addition, R2 increases the equivalent load impedance across TTIP and TRING. RECEIVE CIRCUIT The receive line interface signal is input at the RTIP and RRING binding posts. The receive signal is transformer coupled to the line interface device through a center-tapped 1:2 transformer. The transformer produces ground referenced pulses of equal amplitude and opposite polarity on RTIP and RRING. The receive line interface is terminated by resistors R9 and R10. The evaluation boards are supplied from the factory with 200 resistors for terminating 100 T1 twisted-pair lines. Resistors R9 and R10 should be replaced with 240 resistors for terminating 120 E1 twisted-pair lines or 150 resistors for terminating 75 E1 coaxial lines. Two 243 resistors and two 150 resistors are included with the evaluation board for this purpose.
DS40DB3
The recovered clock and data signals are available on BNC outputs labeled RCLK, RPOS(RDATA), and RNEG(BPV). In the Hardware and Host operating modes, data is output on the RPOS(RDATA) and RNEG(BPV) connectors in dual NRZ format. In the Extended Hardware operating mode, data is output in NRZ format on the RPOS(RDATA) connector and bipolar violations are reported on the RNEG(BPV) connector. QUARTZ CRYSTAL A quartz crystal must be installed in socket Y1 for all devices except the CS6158 and CS6158A. A Crystal Semiconductor CXT6176 crystal is recommended for T1 operation and a CXT8192 is recommended for E1 operation. The evaluation board has a CXT6176 installed at the factory and a CXT8192 is also provided with the board. The CDB6158 and CDB6158A have resistor R13 installed instead of a crystal. This connects the RT pin of the device to the +5 Volt supply. ALTERNATE CLOCK INPUT The ACLKI BNC input provides the alternate clock reference for the line interface device (ACLK for the CS61534) when JP4 is jumpered across C-C. This clock is required for the CS61534, CS61535, CS6158, and CS6158A operation but is optional for all other line interface devices. If ACLKI is provided, it may be desirable to connect both C-C and D-D positions on JP4 to terminate the external clock source providing ACLKI with the 51 resistor R1. If ACLKI is optional and not used, connector JP4 should be jumpered across D-D to ground pin 1 of the device through resistor R1. TRANSFORMER SELECTION To permit the evaluation of other transformers, Table 2 lists the transformer and line interface device combinations that can be used in T1 and E1
37
LINE INTERFACE EVALUATION BOARD
applications. A letter at the intersection of a row and column in Table 2 indicates that the selected transformer is supported for use with the device. The transformer is installed in the evaluation board with pin 1 positioned to match the letter illustrated on the drawing in Table 2. For example, the Pulse Engineering PE-65388 transformer may be used with the transmitter of the CS61575 device for 100 T1 applications only (as indicated by note 3) when installed in transformer socket T1 with pin 1 at position D (upper right). PROTOTYPING AREA A prototyping area with power supply and ground connections is provided on the evaluation board. This area can be used to develop and test a variety of additional circuits like a data pattern generator, CS2180B framer, system synchronizer PLL, or specialized interface logic. EVALUATION HINTS 1. Properly terminate TTIP/TRING when evaluating the transmit output signal. For more information concerning pulse shape evaluation, refer to the Crystal application note entitled "Measurement and Evaluation of Pulse Shapes in T1/E1 Transmission Systems." 2. Change the receiver terminating resistors R9 and R10 when evaluating E1 applications. Resistors R9 and R10 should be replaced with 240 resistors for terminating 120 E1 twisted-pair lines or 150 resistors for terminating 75 E1 coaxial lines. Two 243 resistors and two 150 resistors are included with the evaluation board for this purpose. 3. Closing a DIP switch on S2 towards the label sets the device control pin of the same name to logic 1 (+5 Volts).
4. To avoid damage to the external host controller connected to JP1, all S2 switch positions (except CLKE) should be open. In the Host operating mode, the CLKE switch selects the active edge of SCLK and RCLK.
38
DS40DB3
LINE INTERFACE EVALUATION BOARD
LINE INTERFACE UNIT TRANSFORMER (Turns Ratio)1,2 '34 '35 '35A '58 '58A '74,'77 '74A '75 '304A, '305A RX TX A B D3,5 C3,5 D4,5 C4,5
RX TX RX TX RX TX RX TX RX TX RX TX RX TX RX TX PE-65351 (1:2CT) ADADA ADA ADA A Schott 12930 (1:2CT) BCBCB BCB BCB B PE-65388 (1:1.15) D3 D3 D3 D3 3 3 3 Schott 12931 (1:1.15) C C C C3 PE-65389 (1:1:1.26) D4 D4 D4 D4 4 4 4 Schott 12932 (1:1:1.26) C C C C4 PE-64951 (dual 1:2CT) E E E E Schott 11509 (dual 1:2CT) E E E E PE-65565 (dual 1:1.15 & 1:2CT) E3 E3 E3 E3 Schott 12531 (dual 1:1.15 & 1:2CT) E3 E3 E3 E3 4 4 4 PE-65566 (dual 1:1:1.26 & 1:2CT) E E E E4 4 4 4 Schott 12532 (dual 1:1:1.26 & 1:2CT) E E E E4 NOTES:
E3,5 E3,5 E4,5 E4,5
T2 B
1. A letter at the intersection of a row and column in Table 2 indicates that the selected transformer is supported for use with the device. The transformer is installed in the evaluation board with pin 1 positioned to match the letter illustrated in the drawing to the left. T2 2. The receive transformer (RX) is soldered at location T2 on the evaluation board and is used for all applications. The transmit transformer (TX) is socketed at location T1 on the evaluation board and may be changed according to the application. For use in 75 and 120 E1 applications only. Place jumper JP5 in position F-F for 75 E1 applications requiring a 1:1 turns ratio.
A
D
3. For use in 100 T1 twisted-pair applications only. 4.
C
E T1 T1
5. Transmitter return loss improves when using a 1:2 turns ratio transformer with the appropriate transmit resistors.
Table 2. Transformer Applications
DS40DB3
39
LINE INTERFACE EVALUATION BOARD
Figure 2. Silk Screen Layer (NOT TO SCALE)
40
DS40DB3
LINE INTERFACE EVALUATION BOARD
Figure 3. Top Ground Plane Layer (NOT TO SCALE)
DS40DB3
41
LINE INTERFACE EVALUATION BOARD
Figure 4. Bottom Trace Layer (NOT TO SCALE)
42
DS40DB3
* Notes *
Smart AnalogTM is a Trademark of Crystal Semiconductor Corporation

▲Up To Search▲

Price & Availability of CS61574A

	To Download CS61574A Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .